000			03870naaaa2200385uu 4500
003			BUT
005			20230324120230.0
006			m o d
007			cr|mn|---annan
008			202007s2014 x |||||o ||| eng|| d
040			_aoapen _coapen
041	0		_aeng
080			_a004.7
100	1		_aKundu, Santanu _4auth
245	1	0	_aNetwork-on-Chip _bThe Next Generation of System-on-Chip Integration
260			_bTaylor & Francis _c2014
300			_a1 electronic resource (389 p.)
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
506	0		_aOpen Access _2star _fUnrestricted online access
520			_aAddresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.
540			_aCreative Commons _fhttps://creativecommons.org/licenses/by-nc-nd/4.0/ _2cc
546			_aEnglish
653			_aМикроэлектроника
653			_aКомпьютерная техника
653			_aSCI-TECH
653			_aNoC
653			_aАрхитектурное проектирование сети
700	1		_aChattopadhyay, Santanu _4auth
856	4	0	_awww.oapen.org _uhttps://library.oapen.org/bitstream/id/3347a845-5a35-46b4-80ff-c265283bdae3/9781466565265.pdf _70 _zDownload
856	4	0	_awww.oapen.org _uhttps://library.oapen.org/handle/20.500.12657/41758 _70 _zDescription
909			_c255 _dRobiyakhon Olimjonova
942			_2udc _cEE
999			_c6113 _d6113